Bonded strained semiconductor with a desired surface orientation and conductance direction

ABSTRACT

According to various method embodiments, a semiconductor layer is oriented to a substrate. The semiconductor layer has a surface orientation and is oriented to the substrate to provide a desired direction of conductance for the surface orientation. The oriented semiconductor layer is bonded to the substrate to strain the semiconductor layer. Various embodiments provide a tensile strain, and various embodiments provide a compressive strain. Other aspects and embodiments are provided herein.

PRIORITY APPLICATION

This application is a continuation of U.S. application Ser. No.11/498,586, filed Aug. 3, 2006, which is incorporated herein byreference in its entirety.

TECHNICAL FIELD

This disclosure relates generally to semiconductor structures, and moreparticularly, to strained semiconductor, devices and systems, andmethods of forming the strained semiconductor, devices and systems.

BACKGROUND

The semiconductor industry continues to strive for improvements in thespeed and performance of semiconductor devices. Strained silicontechnology has been shown to enhance carrier mobility in both n-channeland p-channel devices, and thus has been of interest to thesemiconductor industry as a means to improve device speed andperformance. Currently, strained silicon layers are used to increaseelectron mobility in n-channel CMOS transistors. There has been researchand development activity to increase the hole mobility of p-channel CMOStransistors using strained silicon germanium layers on silicon.

FIG. 1A illustrates a known device for improved hole mobility with ann-type silicon substrate 101, a silicon germanium layer 102, a siliconcapping layer 103, a gate oxide 104, a gate 105, and N+ source/drainregions 106 and 107. FIG. 1B illustrates a band structure for the deviceof FIG. 1A, and indicates that some carriers or holes are at thesilicon-oxide interface and some are confined in the silicon germaniumlayer. Both the silicon germanium and the silicon capping layers will bestrained if they are thin. Alternatively, the silicon germanium layermay be graded to a relaxed or unstrained layer resulting in more stressin the silicon cap layer. The crystalline silicon layer is strained by alattice mismatch between the silicon germanium layer and the crystallinesilicon layer.

More recently, strained silicon layers have been fabricated on thickerrelaxed silicon germanium layers to improve the mobility of electrons inNMOS transistors. Structures with strained silicon on silicon germaniumon insulators have been described as well as structures with strainedsilicon over a localized oxide insulator region. These structures yieldhigh mobility and high performance transistors on a low capacitanceinsulating substrate.

Wafer bending has been used to investigate the effect of strain onmobility and distinguish between the effects of biaxial stress anduniaxial stress. Bonding a semiconductor onto bowed or bent substrateshas been disclosed to introduce strain in the semiconductor. Stress canalso be introduced by wafer bonding. Packaging can introduce mechanicalstress by bending. Compressively-strained semiconductor layers have beenbonded to a substrate.

FIGS. 2-4 illustrate some known techniques to strain channels andimprove carrier mobilities in CMOS devices. FIG. 2 illustrates a knowndevice design to improve electron mobility in NMOS transistors using atensile strained silicon layer on silicon germanium. As illustrated, agraded silicon germanium layer 208 is formed on a p-type siliconsubstrate 209 to provide a relaxed silicon germanium region 210, uponwhich a strained silicon layer 211 is grown. The transistor channel isformed in the strained silicon layer 211. There is a large mismatch inthe cell structure between the silicon and silicon germanium layers,which biaxially strains the silicon layer. As illustrated in FIG. 3,uniaxial compressive stress can be introduced in a channel 312 of a PMOStransistor to improve hole mobility using silicon germanium source/drainregions 313 in trenches adjacent to the PMOS transistor. Largeimprovements in hole mobility, up to 50%, have been made in PMOS devicesin silicon technology using strained silicon germanium source/drainregions to compressively strain the transistor channel. Silicon-carbidesource/drain regions in trenches adjacent to an NMOS transistor canintroduce tensile stress and improve electron mobility. FIG. 4illustrates a known device design to improve mobility for both NMOS andPMOS transistors using silicon nitride capping layers 414. These siliconnitride capping layers can be formed to introduce tensile stress forNMOS transistors and can be formed to introduce compressive stress forPMOS transistors.

Another proposal to improve device speed and performance involves highermobility surfaces. For example, it has been proposed to bond unstrained(110) layers of silicon onto (100) surface substrates to improve holemobility in unstrained channel regions of p-channel MOSFETs, and toamorphize the regions in which to fabricate n-channel transistors andrecrystallize the (100) silicon seeded by the underlying (100) substrateto provide the unstrained channel region of n-channel MOSFETs with thehigh channel mobility characteristic of the (100) surface.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates a known device for improved hole mobility, and FIG.1B illustrates a band structure for the device of FIG. 1A.

FIG. 2 illustrates a known device design to improve electron mobility inNMOS transistors using a tensile strained silicon layer on silicongermanium.

FIG. 3 illustrates a known device design to provide uniaxial compressivestress in a channel of a PMOS transistor using silicon germaniumsource/drain regions in trenches adjacent to the PMOS transistor.

FIG. 4 illustrates a known device design to improve mobility for bothNMOS and PMOS transistors using silicon nitride capping layers.

FIGS. 5A-5I illustrate an embodiment where a semiconductor layer isbonded to tensile strain the semiconductor layer.

FIGS. 6A-6K illustrate an embodiment where a semiconductor layer isbonded to compressive strain the semiconductor layer.

FIG. 7 illustrates a top view of a structure in which a plurality oftransistors are being formed, according to various embodiments.

FIGS. 8-14 illustrate various methods for straining semiconductorlayers.

FIG. 15 is a simplified block diagram of a high-level organization of amemory device according to various embodiments.

FIG. 16 illustrates a diagram for an electronic system having one ormore transistors with strained channels for improved mobility, accordingto various embodiments.

FIG. 17 illustrates an embodiment of a system having a controller and amemory, according to various embodiments.

DETAILED DESCRIPTION

The following detailed description refers to the accompanying drawingswhich show, by way of illustration, specific aspects and embodiments inwhich the present subject matter may be practiced. These embodiments aredescribed in sufficient detail to enable those skilled in the art topractice the present subject matter. The various embodiments of thepresent subject matter are not necessarily mutually exclusive as aspectsof one embodiment can be combined with aspects of another embodiment.Other embodiments may be utilized and structural, logical, andelectrical changes may be made without departing from the scope of thepresent subject matter. In the following description, the terms “wafer”and “substrate” are interchangeably used to refer generally to anystructure on which integrated circuits are formed, and also to suchstructures during various stages of integrated circuit fabrication. Bothterms include doped and undoped semiconductors, epitaxial layers of asemiconductor on a supporting semiconductor or insulating material,combinations of such layers, as well as other such structures that areknown in the art. The term “horizontal” as used in this application isdefined as a plane parallel to the conventional plane or surface of awafer or substrate, regardless of the orientation of the wafer orsubstrate. The term “vertical” refers to a direction perpendicular tothe horizontal as defined above. Prepositions, such as “on”, “side”,“higher”, “lower”, “over” and “under” are defined with respect to theconventional plane or surface being on the top surface of the wafer orsubstrate, regardless of the orientation of the wafer or substrate. Thefollowing detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims, along with the full scope of equivalents towhich such claims are entitled.

According to various method embodiments, a semiconductor layer isoriented to a substrate. The semiconductor layer has a surfaceorientation and is oriented to the substrate to provide a desireddirection of conductance for the surface orientation. The orientedsemiconductor layer is bonded to the substrate to strain thesemiconductor layer.

According to various embodiments for forming a transistor, a strainedsemiconductor layer is formed on a substrate, which includes orienting asemiconductor layer to a substrate and bonding the orientedsemiconductor layer to the substrate to strain the semiconductor layer.The semiconductor layer has a surface orientation and is oriented toprovide a desired direction of conductance for the surface orientation.A gate insulator is formed on the strained semiconductor layer, a gateis formed on the gate insulator, and first and second diffusion regionsdefine a channel beneath the gate insulator between the first and seconddiffusion regions.

According to various embodiments for forming a CMOS device, a strainedsemiconductor layer is formed on a substrate. A first semiconductorlayer and a second semiconductor layer are oriented to a substrate. Thefirst semiconductor layer has a first surface orientation and isoriented to provide a first desired direction of conductance for thefirst surface orientation to promote electron mobility. The secondsemiconductor layer has a second surface orientation and is oriented toprovide a second desired direction of conductance for the second surfaceorientation to promote hole mobility. The first and second orientedsemiconductor layers are bonded to the substrate to strain thesemiconductor layer. An n-channel transistor is formed using the firstsemiconductor layer and a p-channel transistor is formed using thesecond semiconductor layer.

Various structure embodiments include a substrate and a crystallinesemiconductor layer bonded to the substrate. The semiconductor layer hasa surface orientation and a desired channel conductance direction forthe surface orientation. The crystalline semiconductor layer has a localstrained region. The structure further includes a gate oxide over thelocal strained region, a gate over the gate oxide, and first and secondsource/drain regions to provide a channel region with the desiredchannel conductance direction within in the local strained region.

For example, strips of silicon of different surface orientations andstrip directions can be bonded onto silicon substrates of varioussurface orientations. The strip direction corresponds to a desireddirection of conduction. In transistor embodiments, the desireddirection of conduction for the strained silicon is the channeldirection. The strips of silicon can be locally strained, and can eitherbe tensile strained during the bonding process to improve the electronmobility and/or can be compressive strained during the bonding processto improve the hole mobility. The improved carrier mobility improvesCMOS transistor performance. The carrier wafer or substrate can be asilicon wafer of any surface orientation, such as the common (100),(110) or (111) silicon substrates.

Tensile Strain Embodiments

FIGS. 5A-5I illustrate an embodiment where a semiconductor layer isbonded to tensile strain the semiconductor layer, such as is provided inU.S. Published Patent Application 20040224480, filed May 7, 2003 andentitled “Micromechanical Strained Semiconductor By Wafer Bonding.” U.S.20040224480 is incorporated by reference herein in its entirety.

FIGS. 5A-5C illustrate a process for forming recesses in a substrateusing a LOCal Oxidation of Silicon (LOCOS) process according to variousembodiments. The LOCOS process is useful to form recesses in siliconsubstrates, and one of ordinary skill in the art will understand, uponreading and comprehending this disclosure, that other methods to formrecesses in substrates can be used for silicon and other substrates.

FIG. 5A illustrates a semiconductor structure 515 toward the beginningof a LOCOS process. The semiconductor structure 515 includes a siliconsubstrate 516. A layer of silicon nitride 517 is deposited, such as byChemical Vapor Deposition (CVD) and the like, on the silicon substrateand is etched to expose portions of the silicon substrate for subsequentselective oxidation. One of ordinary skill in the art will understand,upon reading and comprehending this disclosure, that the pattern of thesilicon nitride affects the pattern and characteristics of the recessesand thus of the strained semiconductor film.

FIG. 5B illustrates the semiconductor structure 515 after the siliconsubstrate 516 has been oxidized. In various embodiments, the oxide 518is thermally grown by means of wet oxidation. The oxide grows wherethere is no masking nitride. At the edges of the nitride, some oxidantdiffuses laterally to grow under the nitride edges. This lateral growthhas the shape of a slowly tapering oxide wedge and is commonly referredto as a “bird's beak.”

FIG. 5C illustrates the semiconductor structure 516 after the oxide hasbeen removed. Recesses 519 remain where the oxidation occurred. Becauseof the formation of the recesses 519, the substrate 516, also referredto as a first wafer, can be referred to as a dimpled substrate as, invarious embodiments, the substrate has a dimpled appearance. As providedbelow, a second wafer, or membrane, is bonded to the substrate such thatportions of the second wafer are strained in the recesses of thesubstrate.

One benefit of the LOCOS process is that it is a common economicalsemiconductor fabrication process. Another benefit of the LOCOS processis the tapered bird's beak, which allows for controlled strain in thefilm. One of ordinary skill in the art will understand, upon reading andcomprehending this disclosure, that the slowly tapering shape of thebird's beak is useful to controllably induce strain in ultra-thinsemiconductor films. However, the tapered bird's beak shape is notrequired to practice the present subject matter. One of ordinary skillin the art will understand, upon reading and comprehending thisdisclosure, that other means for creating a recess or void in thesubstrate can be used. For example, a grinding process can be used tocreate a recess or a trench can be otherwise formed in the substrate.

FIGS. 5D-5H illustrate a method to form a strained semiconductormembrane using a bond cut process to bond a membrane to a substrate withrecesses, according to various embodiments. The bond cut processinvolves bonding together two substrates, or wafers, and breaking off asection of at least one of the two substrate after the substrates havebeen bonded together. The substrate is also referred to herein invarious embodiments as a first wafer or dimpled substrate, and themembrane is also referred to herein in various embodiments as a secondwafer.

FIG. 5D illustrates a sacrificial semiconductor wafer 520, and FIG. 5Eillustrates a semiconductor substrate 516. The substrate 516 includes asemiconductor material, and includes a number of recesses 519, such asillustrated in FIG. 5C. In various embodiments, the semiconductormaterial includes one of the following materials: silicon; germanium;silicon-germanium; gallium arsenide; indium phosphide; and othersemiconductor materials. This list of potential semiconductor materialsis not intended to be an all-inclusive list. The substrate is cut intowafer size patterns, and integrated circuits are formed thereon. Invarious embodiments, the sacrificial wafer includes varioussemiconductor material including but not limited to silicon, germanium,silicon-germanium, gallium arsenide, indium phosphide, and othersemiconductor materials.

The sacrificial wafer 520 is a single crystal wafer, and is conditionedby implanting ions 521 into a surface. The ions are implanted along aplane, represented in FIG. 5D as a line 522, to define a surface layer523 with a predetermined thickness. The plane is approximately parallelto the surface in which the ions are implanted. In various embodiments,hydrogen ions are used as implantation ions. The hydrogen ions caninclude H⁺, H₂ ⁺, D⁺, and/or D₂ ⁺ ions. The implanted ions act to formcavities along the plane 522. The cavities are joined through thermalprocessing, allowing the surface layer 523 to be removed from theremaining portion of the sacrificial wafer 524 at the cleavage plane522. In various embodiments, this thermal processing occurs while thesurface layer 523 is being bonded to the substrate 516, as shown in FIG.5F. Once these cavities join and the surface layer is bonded to thesubstrate, the surface layer breaks off of the sacrificial wafer at thecleavage plane and remains bonded to the substrate. The remainingportion of the sacrificial wafer 524 can be used to form membranes forother substrates, thus reducing the overall cost for the manufacturingprocess of a wide variety of electronic devices.

FIG. 5F illustrates the surface layer 523 of the sacrificial wafer 520bonded to the substrate 516. Before the surface layer is bonded to thesubstrate, the sacrificial wafer and the substrate can be cleaned usingconventional cleaning procedures. In various embodiments, the bondingforce includes the strong Van der Waal's force that naturally bondssurfaces together as the bonding force. In various embodiments, the Vander Waal's force provides an initial bonding force that is strengthenedduring subsequent thermal processing. As illustrated in FIG. 5F, thesurface layer 523 of the sacrificial wafer 520 is bonded to thesubstrate 516 in an environment 525A at a first pressure. In variousembodiments, the first pressure is a vacuum or a low pressure near avacuum.

In various embodiments, the bonded wafers are heated to further bond thesurface layer to the substrate and to cut the surface layer 523 from thesacrificial wafer. In various embodiments, the environment 525A has abonding temperature within a range of approximately 300° C. to 400° C.Heating the sacrificial wafer joins the cavities in the cleavage plane522, allowing the remaining portion 524 of the sacrificial wafer to beremoved from the surface layer, which remains bonded to the substrate.The remaining portion 524 of the sacrificial wafer can be prepared andconditioned for another bond cut process.

The thickness of the surface layer 523 bonded to the substrate 516 isdefined by the depth of ion implantation 521 during the bond cutprocess. In various embodiments, the thickness of the surface layer 523is such that it does not yield or otherwise plastically deform under thedesired mechanical strain induced by the bond. In various embodiments,the thickness of the surface layer 523 is less than 200 nm, such that itcan be termed an ultra thin wafer. In various embodiments, the siliconlayer has a thickness of about 0.1 microns (100 nm or 1000 Å). Invarious embodiments, the silicon layer has a thickness less than 0.1microns. In various embodiments, the silicon layer has a thickness in arange of approximately 300 Å to 1000 Å.

In various embodiments, the silicon film is prepared for transistorfabrication. In various embodiments, the preparation of the filmincludes grinding, polishing, chemical etch, chemical etch with etchstops, and/or plasma assisted chemical etch, and the like, which can beused to further thin the film. Thus, the membrane bonded to thesubstrate illustrated in FIG. 5G can be thinner than the surface layerdefined in the sacrificial layer in FIG. 5D. Device processing can beaccomplished using conventional processes and procedures.

FIG. 5H illustrates the membrane 523 further bonded to the substrate 516in the recesses 519 formed therein. The process is performed in anenvironment 525B having a second temperature. The second pressure isgreater than the first pressure to force the membrane into the recesses.The volume between the membrane and the recessed substrate is a sealedvolume, such that the pressure inside these volumes is approximately thefirst pressure. In various embodiments, the second pressure isatmospheric pressure. In various embodiments, the environment 525B has abonding temperature within a range of approximately 800° C. to 1000° C.The portion of the membrane bonded to the substrate in the recesses isstrained. One of ordinary skill in the art will understand, upon readingand comprehending this disclosure, that the recesses can be made withappropriate dimension to provide a desired tensile strain.

FIG. 5I illustrates a transistor fabricated with a strainedsemiconductor membrane, according to various embodiments. Theillustrated transistor 530 includes a crystalline semiconductorsubstrate 516 with a recess 519, and a crystalline semiconductormembrane 523 bonded to the substrate 516 to provide the membrane 523with a desired tensile strain in the recesses. A gate dielectric 531 isformed on the strained membrane, and a gate 532 is formed on the gatedielectric 531. First and second diffusion regions 533 and 534 areformed in the structure 530. The tensile strained semiconductor membrane523 between the first and second diffusion regions 533 and 534 forms atensile strained channel region 535.

Various embodiments tensile strain a thin semiconductor layer, such as asilicon layer, with a strain greater than 0.5% to achieve significantmobility enhancement. For further mobility enhancement, variousembodiments tensile strain a thin semiconductor wafer, such as anultra-thin silicon wafer with a thickness within a range ofapproximately 300 Å to 1000 Å, with a strain within a range ofapproximately 0.75% to approximately 1.5%. Various embodiments tensilestrain a thin semiconductor layer, such as a thin silicon layer, with astrain in the range of approximately 1% to approximately 1.2% to reduceunnecessary strain and provide a margin of error without undulyaffecting mobility enhancement. In various embodiments, the film isapproximately 1000 Δ or less. In various embodiments, the channel lengthof the transistor is less than or equal to about 1000 Δ, and thethickness of the film is less than or equal to about 300 Δ. The strainenhances mobility in the channel, thus overcoming problems associatedwith heavy channel doping.

Compressive Strain Embodiment

FIGS. 6A-6K illustrate an embodiment where a semiconductor layer isbonded to compressive strain the semiconductor layer, such as isprovided in U.S. patent application Ser. No. 11/356,335, filed Feb. 16,2006 and entitled “Localized Compressive Strained Semiconductor.” U.S.patent application Ser. No. 11/356,335 is incorporated by referenceherein in its entirety. The description that follows refers toembodiments with silicon and silicon dioxide or oxide. However, those ofordinary skill in the art will understand how to implement the teachingsherein with other semiconductors and insulators.

FIG. 6A illustrates a crystalline silicon substrate 636 with a masklayer 637. The mask layer is patterned to define the areas where therewill be localized compressive strain. Thus, the defined areas are usedto provide a channel with compressive strain to improve hole mobilityfor p-channel transistors. In various embodiments, the mask is a siliconnitride. A thin native oxide is between the silicon nitride and thecrystalline silicon substrate.

As illustrated in FIG. 6B, the exposed crystalline silicon 636 is etchedat 638 to a desired depth on each side of the mask 637. A thick oxidelayer 639 is deposited. The resulting structure is planarized, such asmay be performed by a chemical mechanical planarization (CMP) process.The planarizing process stops on the raised silicon areas 640 to leaveislands or strips of silicon 640 embedded in an oxide 639, such as isillustrated in the side view of FIG. 6C and the top view of FIG. 6D.

FIG. 6E illustrates the structure after an oxidation process. The dottedline 641 corresponds to the top surface 641 of the structure illustratedin FIG. 6C, and the dotted lines 642 correspond to the edges 642 of theoxide islands in FIG. 6C. The exposed silicon island 640 oxides rapidly,while the regions covered by the deposited oxide 639 oxidize much moreslowly. The thickness of the deposited oxide and the subsequentoxidation is timed to leave the resulting silicon surface planar underthe oxides of different thickness, and to provide the desired strain, aswill be evident upon reading and comprehending this specification.

FIG. 6F illustrates the structure after the oxide is etched back toexpose the crystalline substrate 643 and reduce the oxide in the islandportion 640 of the oxide. A “bird's beak” is left at the edges of theoxide islands. The bird's beak has a similar shape to that formed by aLOCal Oxidation of Silicon (LOCOS) process. A native oxide 644 forms onthe exposed silicon areas by exposure to air, water or peroxide.

FIGS. 6G-6H illustrate methods for providing an amorphous silicon layerin contact with the crystalline silicon on one side of the oxide island,according to various embodiments. As illustrated in FIG. 6G, anamorphous silicon layer 645 is deposited, and a silicon implant 646breaks up the oxide such that the crystalline silicon substrate at 647is able to seed the crystalline growth of the amorphous silicon layer.As illustrated in FIG. 6H, the native oxide is removed at 647 from oneside of the oxide island and amorphous silicon 645 is deposited andpatterned over the oxide islands. According to various embodiments, thethickness of the silicon film is within a range from approximately 100nm to approximately 200 nm. Such thicknesses are capable of beingmechanically compressed without affecting yield.

FIG. 6I illustrates a recrystallization process for the amorphoussilicon layer, and further illustrates the bonding of the crystallizedlayer after the oxide island is removed. The recrystallization processis also referred to as a solid phase epitaxial (SPE) process, whichincludes depositing a thin amorphous silicon layer and annealing thestructure to recrystallize the amorphous silicon, where one end of theamorphous layer is seeded to promote a desired crystalline growth. Therecrystallization, as illustrated by the arrows 648, is seeded at 647where the silicon layer 645 is in direct contact with the crystallinesilicon substrate 636, and thus only grows from one side since the otherside still has the unperturbed native oxide 643. According to variousembodiments, the silicon film is recrystallized at temperatures fromapproximately 550° C. to approximately 700° C. The transistor channel isformed in this recrystallized silicon strip. The oxide island is etchedfrom underneath the silicon strip to leave an empty space beneath thesilicon strip. As illustrated by the arrow 649, a silicon strip orsilicon bridge layer is influenced toward and bonded to the surfacebeneath the silicon layer. In various embodiments, the naturallyoccurring Van der Waal's force is sufficient to influence the bridgelayer or film 645 into contact with the surface 650 beneath the siliconlayer. In various embodiments, a nano-imprint mask is used to assistwith influencing the film into contact with the surface beneath thesilicon layer.

FIG. 6J illustrates the silicon layer bonded to the surface beneath thesilicon layer. Since the length of the bowed silicon film strip islonger than the planar surface region of the silicon substrate, the film645, now in crystalline form, will be under compressive stress, asillustrated by the arrows 651, after bonding to the substrate surface.

FIG. 6K illustrates a PMOS transistor 652 fabricated in the structureformed with crystalline silicon under compression. The remaining stepsin the PMOS transistor fabrication can be achieved by conventionaltechniques, in which the compressively-strained ultra-thin silicon strip645 forms the transistor channel region. For example, a gate insulator653, such as silicon oxide or other gate insulator, is formed on thestructure, a gate 654 is formed on the gate insulator, and source/drainregions 655 are formed to define a channel 645 beneath the gate andbetween the source/drain regions. The source/drain regions can be formedby an ion implantation process.

Locally Strained Semiconductor Embodiment

FIG. 7 illustrates a top view of a structure in which a plurality oftransistors are being formed, according to various embodiments. Theoxide 756 is illustrated by the dotted line and the pattern of siliconstrips 757 is also illustrated. In another embodiment, a number of oxideregions are combined in the column direction to form one oxide area. Forexample, the column of oxide regions 756A-756E can be formed as oneoxide area. As discussed above, these oxide areas can be used to providea local tensile strain to the silicon strips or a local compressivestrain to the silicon strips. According to various embodiments, the samesubstrate includes silicon strips with both locally tensile strainedregions to promote electron mobility and locally compressive strainedregions to promote hole mobility.

Surface Orientation/Conductance Direction

FIGS. 8-13 illustrate various methods for straining semiconductorlayers. With reference to the embodiment illustrated in FIG. 8, asillustrated at 858 a semiconductor layer is oriented to a substrate toprovide a desired direction of conductance of a surface orientation ofthe semiconductor layer. In embodiments in which strips of semiconductorare bonded to the substrate, the strips are formed in the direction ofconductance. Other embodiments use larger membranes or films. Thesurface crystal orientation is conventionally provided using Millerindices in parentheses. The direction of conduction is provided using XY Z coordinates in angle brackets, and is based on the same coordinatesystem used to identify the surface orientation of the semiconductorlayer. For a given surface crystal orientation, some directions are moreconductive than others. At 859, the oriented semiconductor layer isbonded to the substrate to strain the semiconductor layer. Variousembodiments induce a compressive strain and various embodiments induce atensile strain when the layer is bonded to the substrate. The thicknessof the layer is sufficiently thin to permit the strain without yield.Various embodiments create the layer using a bond cut process, such asillustrated in FIGS. 5D-5G. Various embodiments remove the back of asacrificial wafer, which has been bonded to the substrate, by amechanical and chemical etch procedure. Various embodiments create thelayer by depositing an amorphous layer and recrystallizing the layerusing a solid phase epitaxial process, such as illustrated in FIGS.6G-I.

FIG. 9 illustrates an embodiment of a method of bonding a (100) siliconlayer to provide desired conductance in the <110> direction. Inembodiments in which strips of silicon are bonded to the substrate, thestrips are formed in the <110> direction. At 958, a (100) silicon layeris oriented to a substrate to provide a <110> direction of conductancefor the (100) silicon layer. At 959, the oriented (100) silicon layer isbonded to the substrate to strain the silicon layer. Various embodimentsbond the layer onto raised oxide areas on any carrier wafer to improvehole mobility by removing the oxide from under the strips and completingthe bonding to leave the strip in compressive stress. Variousembodiments bond the silicon layer over recessed oxide areas on anycarrier wafer to improve electron mobility by removing the oxide fromunder the strips and completing the bonding to leave the strip intensile stress.

FIG. 10 illustrates an embodiment of a method of bonding a (110) siliconlayer to provide desired conductance in the <100> direction. Otherdirections of conductance can be used with respect to the (110) siliconlayer. In embodiments in which strips of silicon are bonded to thesubstrate, the strips are formed in the <100> direction. At 1058, a(110) silicon layer is oriented to a substrate to provide a <100>direction of conductance for the (110) silicon layer. At 1059, theoriented (110) silicon layer is bonded to the substrate to strain thesilicon layer. Various embodiments bond the layer onto raised oxideareas on any carrier wafer to improve hole mobility by removing theoxide from under the strips and completing the bonding to leave thestrip in compressive stress. Various embodiments bond the silicon layerover recessed oxide areas on any carrier wafer to improve electronmobility by removing the oxide from under the strips and completing thebonding to leave the strip in tensile stress.

FIG. 11 illustrates an embodiment of a method of bonding a (111) siliconlayer to provide desired conductance in the <110> direction. Inembodiments in which strips of silicon are bonded to the substrate, thestrips are formed in the <110> direction. At 1158, a (111) silicon layeris oriented to a substrate to provide a <110> direction of conductancefor the (111) silicon layer. At 1159, the oriented (111) silicon layeris bonded to the substrate to strain the silicon layer. Variousembodiments bond the layer onto raised oxide areas on any carrier waferto improve hole mobility by removing the oxide from under the strips andcompleting the bonding to leave the strip in compressive stress. Variousembodiments bond the silicon layer over recessed oxide areas on anycarrier wafer to improve electron mobility by removing the oxide fromunder the strips and completing the bonding to leave the strip intensile stress.

FIG. 12 illustrates an embodiment of a method of bonding (100) siliconlayers to provide desired conductance in the <110> direction. Asillustrated at 1258A and 1259A, a first (100) silicon layer is orientedto a substrate to provide a <110> direction of conductance of the first(100) silicon layer, and the first (100) silicon layer is bonded to thesubstrate to tensile strain the first silicon layer. As illustrated in1258B and 1259B, a second (100) silicon layer is oriented to a substrateto provide a <110> direction of conductance of the first (100) siliconlayer, and the second (100) silicon layer is bonded to the substrate tocompressive strain the second silicon layer. Thus, on a same substrate,the strips with local tensile stress improve the mobility of n-channelMOSFETs and the strips with local compressive stress improve holemobility of p-channel MOSFETs. Thus, the present subject matter can beimplemented in CMOS design.

FIG. 13 illustrates an embodiment of a method of bonding a (100) siliconlayer to provide a desired conductance in the <110> direction andbonding a (110) silicon layer to provide a desired conductance in the<100> direction. At 1358, a (100) silicon layer is oriented to asubstrate to provide a <110> direction of conductance and a (110)silicon layer is oriented to the substrate to provide a <100> directionof conductance. At 1359, the oriented (100) silicon layer and theoriented (110) silicon layer are bonded to the substrate to strain thesemiconductor layers. Local strain for either the (100) layer or the(110) layer can be either tensile strain or compressive strain. Since inthis case the strips will all have the same height above the smoothsurface of the carrier wafer the backs of the strips can also bemechanically polished as well as chemically polished. Removing the oxidefrom under the strips and completing the bonding will leave the stripsin tensile stress improving the mobility of both electrons and holes inMOSFETs. The MOSFETs can be fabricated using conventional techniques.

The direction of a uniaxial strain can affect the carrier mobility. Forexample, as reported by Irie et al., “In-Plane Mobility Anisotropy andUniversality Under Uni-Axial Strains In N- and P-MOS Inversion Layers On(100), (110), and (111) Si,” IEDM Technical Digest, 13-15 Dec. 2004, pp.224-228, a <110> channel direction and a tensile strain direction in the<110> direction is desirable for improved electron mobility in a (100)silicon layer and a <100> channel direction and a tensile strain in the<100> direction is desirable for improved hole mobility in a (110)silicon layer. Thus, various embodiments uniaxially strain thesemiconductor layer in a desired direction with respect to the desireddirection for conduction to improve carrier mobility. With reference toFIG. 14, at 1458 a semiconductor layer is oriented to a substrate toprovide a desired direction of conductance for a surface orientation ofthe semiconductor layer. At 1459 the oriented semiconductor layer isbonded to the substrate to strain the semiconductor layer. Asillustrated by 1460, the bonding process includes uniaxially strainingthe semiconductor layer in a desired direction with respect to thedesired direction of conduction to improve conductance.

Device/System Embodiments

FIG. 15 is a simplified block diagram of a high-level organization ofvarious embodiments of a memory device according to various embodimentsof the present subject matter. The illustrated memory device 1561includes a memory array 1562 and read/write control circuitry 1563 toperform operations on the memory array via communication line(s) orchannel(s) 1564. The illustrated memory device 1561 may be a memory cardor a memory module such as a single inline memory module (SIMM) and dualinline memory module (DIMM). One of ordinary skill in the art willunderstand, upon reading and comprehending this disclosure, thatsemiconductor components in the memory array and/or the controlcircuitry are able to be fabricated using the strained semiconductor, asdescribed above. For example, in various embodiments, the memory arrayand/or the control circuitry include p-channel transistors with improvedhole mobility and/or n-channel transistors with improved electronmobility, as disclosed herein. The structure and fabrication methods forthese devices have been described above.

The illustrated memory array 1562 includes a number of memory cells 1565arranged in rows and columns, where word lines 1566 connect the memorycells in the rows and bit lines 1567 connect the memory cells in thecolumns. The read/write control circuitry 1563 includes word line selectcircuitry 1568, which functions to select a desired row. The read/writecontrol circuitry 1563 further includes bit line select circuitry 1569,which functions to select a desired column. The read/write controlcircuitry 1563 further includes read circuitry 1570, which functions todetect a memory state for a selected memory cell in the memory array1562.

FIG. 16 illustrates a diagram for an electronic system having one ormore transistors with strained channels for improved mobility, accordingto various embodiments of the present subject matter. Electronic system1671 includes a controller 1672, a bus 1673, and an electronic device1674, where the bus 1673 provides communication channels between thecontroller 1672 and the electronic device 1674. In various embodiments,the controller and/or electronic device include p-channel transistorswith improved hole mobility and/or n-channel transistors with improvedelectron mobility, as disclosed herein. The illustrated electronicsystem 1671 may include, but is not limited to, information handlingdevices, wireless systems, telecommunication systems, fiber opticsystems, electro-optic systems, and computers.

FIG. 17 illustrates an embodiment of a system 1775 having a controller1776 and a memory 1777, according to various embodiments of the presentsubject matter. The controller 1776 and/or memory 1777 may includep-channel transistors with improved hole mobility and/or n-channeltransistors with improved electron mobility, as disclosed herein. Theillustrated system 1775 also includes an electronic apparatus 1778 and abus 1779 to provide communication channel(s) between the controller andthe electronic apparatus, and between the controller and the memory. Thebus may include an address, a data bus, and a control bus, eachindependently configured; or may use common communication channels toprovide address, data, and/or control, the use of which is regulated bythe controller. In an embodiment, the electronic apparatus 1778 may beadditional memory configured similar to memory 1777. An embodiment mayinclude a peripheral device or devices 1780 coupled to the bus 1779.Peripheral devices may include displays, additional storage memory, orother control devices that may operate in conjunction with thecontroller and/or the memory. In an embodiment, the controller is aprocessor. Any of the controller 1776, the memory 1777, the electronicapparatus 1778, and the peripheral devices 1780 may include p-channeltransistors with improved hole mobility and/or n-channel transistorswith improved electron mobility, as disclosed herein. The system 1775may include, but is not limited to, information handling devices,telecommunication systems, and computers. Applications containingstrained semiconductor films as described in this disclosure includeelectronic systems for use in memory modules, device drivers, powermodules, communication modems, processor modules, andapplication-specific modules, and may include multilayer, multichipmodules. Such circuitry can further be a subcomponent of a variety ofelectronic systems, such as cameras, video recorders and players,televisions, displays, games, phones, clocks, personal computers,wireless devices, automobiles, aircrafts, industrial control systems,and others.

The memory may be realized as a memory device containing p-channeltransistors with improved hole mobility and/or n-channel transistorswith improved electron mobility, as disclosed herein. It will beunderstood that embodiments are equally applicable to any size and typeof memory circuit and are not intended to be limited to a particulartype of memory device. Memory types include a DRAM, SRAM (Static RandomAccess Memory) or Flash memories.

Additionally, the DRAM could be a synchronous DRAM commonly referred toas SGRAM (Synchronous Graphics Random Access Memory), SDRAM (SynchronousDynamic Random Access Memory), SDRAM II, and DDR SDRAM (Double Data RateSDRAM).

This disclosure includes several processes, circuit diagrams, andsemiconductor structures. The present subject matter is not limited to aparticular process order or logical arrangement. Although specificembodiments have been illustrated and described herein, it will beappreciated by those of ordinary skill in the art that any arrangementwhich is calculated to achieve the same purpose may be substituted forthe specific embodiments shown. This application is intended to coveradaptations or variations of the present subject matter. It is to beunderstood that the above description is intended to be illustrative,and not restrictive. Combinations of the above embodiments, and otherembodiments, will be apparent to those of skill in the art uponreviewing the above description. The scope of the present subject mattershould be determined with reference to the appended claims, along withthe full scope of equivalents to which such claims are entitled.

What is claimed is:
 1. A structure, comprising: a substrate; acrystalline semiconductor layer bonded to the substrate, thesemiconductor layer having a surface orientation and a desired channelconductance direction for the surface orientation, the crystallinesemiconductor layer having a local strained region; and a gate oxideover the local strained region, a gate over the gate oxide, and firstand second source/drain regions to provide a channel region with thedesired channel conductance direction within in the local strainedregion.
 2. The structure of claim 1, wherein the local strained regionincludes a uniaxial tensile strain.
 3. The structure of claim 1, whereinthe local strained region includes a uniaxial compressive strain.
 4. Thestructure of claim 1, wherein the crystalline semiconductor layerincludes a silicon layer with a (100) crystalline orientation and thedesired channel conductance direction is a <110> direction with respectto the crystalline orientation.
 5. The structure of claim 1, wherein thecrystalline semiconductor layer includes a silicon layer with a (110)crystalline orientation and the desired channel conductance direction isa <100> direction with respect to the crystalline orientation.
 6. Thestructure of claim 1, wherein the crystalline semiconductor layerincludes a silicon layer with a (111) crystalline orientation and thedesired channel conductance direction is a <110> direction with respectto the crystalline orientation.
 7. The structure of claim 1, wherein thecrystalline semiconductor layer includes a silicon layer with a (100)crystalline orientation and the desired channel conductance direction isa <100> direction with respect to the crystalline orientation.
 8. Thestructure of claim 1, wherein the local strained region has a straingreater than 0.75%.
 9. The structure of claim 1, wherein the localstrained region has a strain within a range between approximately 0.75%and approximately 1.5%.
 10. The structure of claim 1, wherein the localstrained region has a strain within a range between approximately 1.0%and approximately 1.2%.
 11. The structure of claim 1, wherein thecrystalline semiconductor layer has a thickness of approximately 1000 Åor less.
 12. The structure of claim 1, wherein the crystallinesemiconductor layer has a thickness of approximately 300 Å to 1000 Å.13. A structure, comprising: a substrate; a crystalline silicon layerbonded to the substrate, the semiconductor layer having a thickness ofapproximately 1000 Å or less and having a surface orientation and adesired channel conductance direction for the surface orientation, thecrystalline semiconductor layer having a local strained region thatincludes a uniaxial strain; and a gate oxide over the local strainedregion, a gate over the gate oxide, and first and second source/drainregions to provide a channel region with the desired channel conductancedirection within in the local strained region.
 14. The structure ofclaim 13, wherein the uniaxial strain is compressive.
 15. The structureof claim 13, wherein the uniaxial strain is tensile.
 16. The structureof claim 13, wherein the local strained region has a strain within arange between approximately 0.75% and approximately 1.5%.
 17. Thestructure of claim 13, wherein the local strain region includes a firstlocal strain region that includes a tensile strain, the structurefurther including a second local strain region that includes acompressive strain.
 18. A structure, comprising: a substrate; a firstcrystalline silicon layer bonded to the substrate, the first layerhaving a first surface orientation and a first desired channelconductance direction for the first surface orientation, the first layerhaving a first local strained region; a first device formed using thefirst layer, including a first gate oxide over the first local strainedregion, a first gate over the first gate oxide, and first and secondsource/drain regions to provide a first channel region with the firstdesired channel conductance direction within in the first local strainedregion; a second crystalline silicon layer bonded to the substrate, thesecond layer having a second surface orientation and a second desiredchannel conductance direction for the second surface orientation, thesecond layer having a second local strained region; and a second deviceformed using the second layer, including a second gate oxide over thesecond local strained region, a second gate over the second gate oxide,and third and fourth source/drain regions to provide a second channelregion with the second desired channel conductance direction within inthe second local strained region.
 19. The structure of claim 18, whereinthe first layer is a (100) silicon layer, the first desired channelconductance is in the <110> direction with respect to the (100) siliconlayer, the second layer is (110) silicon layer, and the second desiredchannel conductance is in the <100> direction with respect to the (110)silicon layer.
 20. The structure of claim 18, wherein the first localstrained region includes a tensile strain and the second local strainedregion includes a compressive strain.